Multi-tone arpeggio system for electronic organ

ABSTRACT

An automatic arpeggio system for an electronic organ, in which playing of a chord, or a single note, turns on tone signal gates for the played notes, and, at will, all octavely related notes, and initiates action of an assynchronous up-down multi-stage counter which sequentially reads out only the turned on gates, in sequence, either in an up-scan only, or up and then down. The gates lead to tone color filters, amplifiers and loudspeakers. Those counter stages which are selected to turn on gates are constrained to act as clock controlled bistable flip-flops, while the remainder act as monostable flip-flops with a time constant of the order of 30 microseconds, so that their set and reset involves inadequate time elapse to effect sounding of a note by closing of a tone gate.

- United StatesPatent 1191 Bunger 1 v July 2, 1974 MULTl-TONE ARPEGGIO SYSTEM F0 1,243,720 7/1967 Germ 4...; 307/222 ELECTRONIC ORGAN 1,204,708 11/1965 Germany 307/222 lnventor: David A. Bunger, Cincinnati, Ohio 1 i [73] Assignee: D. H. Baldwin Company, Cincinnati, Primary Exammer j.ohn Heyman Ohio Attorney, Agent, or Frrm-Hyman Hurvltz -22] Filed: Nov. 10, 1972' I i 1 11 pp 5, 1 4 '57 ABSTRACT Related U.S. Application Data r 1 [62] Division of Ser No 171-879 Aug 16 1971 Pat No C alitomanqarpggglo System for electromc Organ 3 718 748 v 1n which playing of a chord, or a smgle note, turns on f 1 tone signal gates for the played notes, and, at will, all [52] U S Cl 328/42 328/44 307/273 octavely related notes, and initiates action of an assyn- 0 6 328/48 chronous up-down multi-stage counter which sequen- 51 lm. c1. H03k 21/32 reads out lined gates in sequence 58 Field of Search 307/222 221, 273, 292'- elthe? m up'scan only and down- The 48 ;gates leadto tone color filters, amplifiers and loud- 3 speakers. Those counter stages which are selected to d to act as clock con- [56] References Cited onpgates m? trolled bistable fl1p-flops, wh1le the remamder act as I STATES PATENTS monostable flip-flops with a time constant of the or'de-r Kmtner microseconds so their Setand reset involves L737 S0112 307/222 inadequate time elapse to effect sounding of a note by 3,388,319 6/1968 Paynter 307/222- closing o a tone gateh FOREIGN PATENTS OR APPLICATIONS I 637,195 2/1962 Canada 307/222 19 Claims, 8 Drawing Figures FROi ILO UEROCTHNE D I ff-I flu T m wmmen g r 5v i 1 I 1: ll -25VDC i 81 4. I i 3 i CLOCK c1. V 1 .2 A m k i m .1 K i COUNTERFL1P-FLOP I 1 magi-" m? r-- a. 53,--. 1 !*;3. 1. 1 1 m NnlEQi F NUTES: M} m 11 m P117 I k l 3 r4 INK I I59 I I znsvvi E? k =3 G3 DST-1F ;TuFOLLow1uG T] I $TAGE 1 1 1 1 1; w 1215 u fli n W 14 ILJ'ZD'I 2D] 1 UP com-e01. SGNHL sieum. \NPUTS 1301 m {n 131 J GATE 'ZUI 5120M FQRQMJL v 2119 3 5mm GATE 1m Gal "1.

3 TBNE T215 16 W03 36 i C LOCK OUTPU F M MU E PLAY ED DETECTOR EXP. PE DRL.

' MULTI-TONE ARPEGGIO SYSTEM FOR ELECTRONIC ORGAN This is a division, of application Ser. No. 171,879, filed'Aug. 16, 1971, now US. Pat.- No. 3,718,748.

BACKGROUND lizing a ramp voltage for scanning the tone output gates of an electronic organ upwardly, and a triangular voltage wave for the up-down mode. The ramp or triangular wave must sequentiallyscan all possible notes which are called forth in an organ employing the system, plus all notes of corresponding nomenclatures, but must pass over all other notes. To accomplish this, a string of series connected diodes is scanned by the ramp voltage, certain of which, corresponding with non-called for notes, are shorted, and the others left open circuited in response to playing of keys. This has the effectof eminating only the shorted diodes from the system during any scan, up or down, but scanning of the unshorted diodes sounds notes.- When the ramp has ups'canned through the last of the conductive diodes, it can be caused to reverse and to scan the diodes in a descending sense, or it can be set for a further up-scan, and the'slope of'the ramp or triangular wave establishes the tempo of the arpeggio.

- In the system of'the present invention, the ramp and diode scanning system is replaced by an up-down as synchronous counter chain, acting as a commutator. Certain of the flip-flop elements of which, corresponding to uncalled for notes and notes octavely related to the latter, are scanned through so rapidly that no sound is heard, whereas the actuated keys effect a sufficiently slow per stage operation that corresponding sounds are heard. The counter is constituted of flip-flops which have two modes of operation, depending on whether or not an associated key of an organ is actuated. In one mode of operation the flip-flop acts as a mono-stable device with an operating time of about 30. microsec-' onds. When a key is actuated, the associated flip-flop is made bistable, and is timed by a clock. The temp of. an arpeggionis therefore controllable in terms of clock frequency.

SUMMARY OF THE INVENTION A system for automatically generating arpeggios and strums in an electronic organ, including an up-down counter composed of a chain of flip-flops which can be individually set to operate monostably or bistably, and aclock to time the bistable stages, used to sequentially open tone gates for preset durations. Those flip-flops which relate to actuated keys of the organ and notes of the same nomenclature but higher in pitch are operated as bistable devices controlled by the clock, and those relating to un-actuated keys operate as mono-stable devices of very short time constant (30. microseconds) independent of the clock. Controls are provided which establish various operational modes of the system l a normal mode, 'in which tones sound as played; (2) a strum mode, in which notes directly called for by ac- ,tuated keys are played in Lip-sequence only; (3) an uparpeggio mode in which all notes of a given nomencla- 2 ture including those of higher octaves and the same nomenclature, called for by actuating a key or keys, are played in an up-arpeggio sequence; (4) an up-down arpeggio mode, in which each sequence (3) is automatically followed by a down arpeggio, involving the notes called for by the actuated keys. The down arpeggio can be interrupted and the up-arpeggio reestablished by playing a note or notes during the down arpeggio; (5)

a multi-tone mode which can be used in conjunction with theabove strum mode or either arpeggio mode, in which the actuation of a key during a strum or arpeggio sequence introducesan additional strum or arpeggio sequence. Since notes can be added to or subtracted from'any up arpeggio, or added to or subtracted from a called-for sequence, during any down arpeggio, simultaneous complex arpeggiosequences of tones can be induced, in the (5) mode, though all must proceed in the same direction at any given time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is largely a block diagram of a system for automatically generating arpeggiosaccording to the invention, and duplicates FIG. l of Bunger, Ser. No. 102,874, referred to hereinabove;

FIG. 2 is a circuit diagram of certain controls employed in the system of FIG. 1;

FIG. 3A and 3B taken together constitute a circuit diagram of an up-down counter and controls therefor,

corresponding with the block diagram of FIG. land responsive to the controls of FIG. 2;

FIG. 4 is a logic diagram of the system ,of FIGS. 3A, 3B I FIG. '5 is atone flow diagram of the system of FIGS. 3A, 3B; I

. FIG. 6 is a circuit diagram of an alternative pedal controlled clock, utilizable in the systernof FIGS. 3A,

3B; and

FIG. 7 is a circuit diagram of a system for avoiding double topnotes in up-down arpeggios.

DETAILED DESCRIPTION OF THE DRAWINGS In FIG. 1, key switches 10 are illustrated and are labeled in respect to the notes called for. A positive voltlatter is a multi-stage cou'nter.

Each key has a signal gate, as 23, for C2, 24 for C2 and each signal gate is connected to a tone signal source, as 25 for C2, which is of appropriate frequency,

and of square wave character in the usual case. These key gates 23, 24 etc., are all short sustain gates, to enable staccato piano simulation. Long sustain piano effects are achieved by connecting a long sustain gate in cascade with each short sustain gate, as in US. patent application Ser. No. 102,874, filed in the name of David A. Bunger and assigned to the assignee of this application.

All C switches of a manual connect to a bus 30, all C switches to a bus 31- and all D switches to a bus 32, in each case via anisolating resistance 34, and so on for the remaining notes. There are therefore four sets of three busses'per set to cover all the octaves and all the notes of each octave, each octave being divided into four sets of three adjacent notes per set, three having been selected as economical, and not as a matter of principle. Only one set of busses is illustrated. There thus is provided a C bus, to which all Cs are connected, a C bus to which all C S are connected, and so on, and it is these busses, rather than the key switches that are connected to key on the signal gates, as C2, C2 D2. The latter set has its outputs tied together at a common output terminal 35, and the signal output ter minals 24b lead to tone gates 36, 37, 38, 39, etc., which .have long sustain capability. The latter four gates cover the first octave, but each octave has its'set of four tone gates. A total of twelve tone gates is illustrated, but to cover an organ keyboard of 61 notes, 20 tone gates are employed, the highest frequency tone gate collecting signal from four, instead of the usual three, signal gates. All the tone gates of the system lead to a common bus.

40, which in turn proceeds to tab selected tone filters 14,.conventional in electronic organs. The filters lead to amplifier l5 and loudspeaker 16. The tone gates are turned on or read out in sequence by sequential readout 13, for the arpeggio mode of the system, or for the strum mode, in which a guitar is simulated. If the piano mode is desired, sequential readout is disabled and all energized tone gates are enabled simultaneously, by

means not shown in FIG. 1. However, the readout is so accomplished that only tone gates which have signal present at their input are read out, or scanned, and the others are effectively skipped.

' The sequential readout has a limited number of readout positions, specifically 20, there being one readout position for each of tone gates 36, 37, etc. Each readout position is enabled or disabled, according to a control voltage on each of leads 45, 46, etc., which proceed each from a group of three key switches, as C2, C2 D. If a position is enabled it is read out in sequence, but if not it is skipped so that any called for notes can be read out in orderly note sequence regardless of how randomly they may be positioned in the array of all possible notes. The speed of readout can be controlled at will. This readout controls and effects arpeggiation.

The busses 30, 31, 32 are divided into octave sections by series diodes 51 and shunt diodes 53. For example, the C bus starts with'the C2 switch It), and proceeds via a resistance 50,'and a series of diode 51, conductively as 51, are conductive, and all notes of the same nomenclature are then represented on bus 30, when they fall above the note actually called forth. However, if a note in the 3 octave is called for, the diode 51 acts to isolate the 2 octave gates, because of the polarity of diode '51. Therefore, 'all notes of a given nomenclature, called for by an actuated key, for all octaves above that key, are simultaneously gated on by the key, but no notes of that nomenclature in lower octaves are gated If the cathodes of shunt diodes 53 are grounded, by grounding bus 54, at switch 12, no octaves are gated on which are higher or lower than the octave being played in, since a series diode isolates the lower octaves, and a shunt diode isolates the higher octaves. However, a

player can have a chord spanning two octaves, and all played notes will be heard together, either in the piano mode if that is called for, or sequentially in any of the remaining modes, up only or up-down as called for, by appropriate switches, hereinafter described.

It is evident that separate controls could have been provided for each separate set of three shunt diodes 53, if desired, and also that a sequential readout could have been provided for each signal gate, if desired, instead of for each set of three. The design actually selected presents a compromise between cost or complexity, and performance, which is justified by musical and economic realities.

Referring to FIG. 2, 71 is a flip-flop or counter stage (of which there are 20 in the present embodiment of the invention) which has two modes of operation, depending on the status .of three key switches associated with the stage (four-in the case of the twentieth flipflop). Three signal gates, shown in FIG. 1 as 23, 24, 24a, are illustrated 'at 72. It is necessary that any of the three notes, on an OR basis, control the state of counter stage 71, so that any andevery note called for be sounded, but it is also necessary that when a lower octave note is keyed, higher octave signal gates are actuated as well as the signal gate pertaining directly to the actuated key. Circuits for the latter purpose are illustrated in FIG. 1.

Signal inputs to the tone gate 36 are derived from three adjacent notes, as C2, C2 D2, and each set of three notes in the system requires a tone gate, except for the highest four notes, which utilize a single tone gate.

A positive voltage source is available at lead U, which is conveyed via any one or more of key switches 10, identified as S S S to terminal 74, and thence to the collector of transistor Q1, of flip-flop N, shown as 71. This transistor is normally on and Q of flip-flop 71 is normally off. If voltage is applied to collector of 0,, the flip-flop will act as a bistable flip-flop. If none of the key switches is closed, transistor 01 has no collector supply and the stage acts as a monostable device with a time constant of about 30. microseconds.

The trigger input to flip-flop 71 is a short duty cycle rectangular wave applied at T, from the clock.

Before proceeding further with details of circuitry,

reference is made to FIGS. 4 and 5, of the accompanying drawings, where the logic of the present system is illustrated, in respect to control signals in FIG. 4 and tone signals in FIG. 5. KS is a series of key switches No. 13 No. 73 of an electronic organ. Discussing key switches No. 13, No. 14, and No. 15, each supplies gat ing voltage, as via a lead 100, to a three signal gate SG, (23, 24, 25a of FIG. 1) pertaining to three keys, which sum and pass tone signal to tone' gate TGl via a single lead (shown in FIG. 5). Twenty signal gates SG1-SG20 are illustrated to encompass 61 key switches, SG 20 pertaining to the highest four key switches, and SG1 to SGI9 to three key switches each.

The tone signal paths are illustrated in FIG. 5. Each tone gate is a linear gate of known type and carries, without intermodulation, one, two, or three tone signals, according to which key or keys are actuated. In addition each signal gate, SG1 SG20, controls signal gates an octave above itself, in respect to notes of the same nomenclature, as indicated by leads 102 in FIG. 4. So SG1 primes 8G5, which' primes SG9, which primes SG l3,'etc. The circuits required are illustrated fier serving two tone gates. The tone gates are normally open (noncondu'ctive) and are closed by signal on a lead 70 from terminal Oofthe associated counter stage (FIG. 2). The sustain time of the tone gate is controlled .by sustain circuit 1073(FIG. 4) which is turned on whenever any associated key switch of KS is closed, in response to anote played detector 108 which senses the'playing of any note as a voltage variation.

Whenever one of SG1-SG20 is operated by playing one or more of thenotes of the gate a latch-in voltage is applied to the appertaining counter stage Cl-C20 via a lead 45, which transfers that stage from its normal configuration as a monostable flip-flop, which stays on for only a few microseconds when triggered, to a bistable flip-flop which must bereset or'timed by a clock CL. The note played detector 108 supplies a variety of signals via lead 110,i.e., a 20. microsecond pulse to the first stage C1 to initiate a scancycle of the counter, at lead 111, a +D.C. voltage to. an enableor start control circuit 112, which supplies voltage via lead 113 which enables thecounter C1 to respond to-the pulse on lead 111. The latter so operates that once the counter starts it can complete its up sequence regardless of whether or not a new key is depressed during the up sequence, in normal up arpeggio or strum model The start control 112 also serves to enable start of a cycle of the counter, for example, if all controlling key switches are opened.

vThe time between the playing of notes is established by a clock CL, normally inoperative,v but which is started into operation and terminated via D.C. control signal on lead 115, the latter being supplied from lead 110. This +D.C. signal is the same as is supplied to start control 112.

The counter Cl-,C20 can count up or down, i.e., it is reversible, according to the character of a control voltage supplied by up-down flip-flop 116. The bus 110 supplies a pulse to up-down flip-flop 116 when a note is played, to assure that it isin the up state, and will therefore cause the counter chain always to count up immediately after a key is depressed.

A manual switch 120 supplies signal from the last counter C20 of the chain, selectively, to a lead 121 or a lead. 123, selectively. If to lead 121, a pulse is supplied toup-down flip-flop 116 from counter C20 which transfers the entire counter chain into a downwardly counting'chain, and at the same time transfers information to the start control 112 via lead 122 which will permit the next pulse from C1, signifying termination of a down count, to set the start control in a state which allows the introduction of a new pulse from lead 110 into the counter chain at C1, thereby initiating a new up count sequence.

If switch 120 is in its down position an output pulse at C20, signalling that the counter chain C1-C20 has completed an up sequence, proceeds via lead 123 to start control 112 and sets it forthwith in condition for a new sequence of up counts, starting at C1.

Sustain control 107 supplies a sustain control signal via lead to a common gate 126. This gate is triggered on via voltage on lead 127 connected to common bus 105, which is supplied with a pulse as each note of gates NGl-NG20 is turned on by counter chain C1-C20, via leads 127a.

The present system has five modes of operation, called for purpose of identification, (1) normal (2) strum (3) arpeggio up (4) arpeggio up and down 5) multi-note. t

In the normal mode no arpeggio is desired, but the instrument responds to each key as it is actuated. -25V is applied via switch 130 to lead l3l, common to all the counters. This converts the counter stages to a mode in which they are essentially pulse amplifiers. Therefore, any note played transfers a gatingpulse from S6,, to C, to a tone gate T0,, (subscript n indicating a typical stage), which transfers that note to one signal amplifier, say 105 (FIG. 5) for notes 13, 14, 15, and thenote is sounded.-Another output of each-TG gate proceeds to lead'105 (FIG. 4), which operates common gate 126, which transmits notes which. ave passed through a tone color filter. 1

The clock CL, when the switch 130 connects it to lead 1311, applies a positivepulse to the counter stages and these then if bistable, are timed. The clock CL is normally inoperative, and starts operation in response to playing of a note, which causes +D.C. to be applied to the clock CL via lead 115. t

The strum mode isthe same as the arpeggio-up mode, except that only notes actually played produce sounds, and higher octave notes are not sounded. Ittherefore corresponds with a limited range arpeggio-L To illustrate what occurs we may assume that two notes are played simultaneously, one encompassed by three note gates SG1 and the other by $62. If both were encompassed by SG1, for example, they would sound together, and no strum effect would occur. But,

if both SG1 and 862 are actuated, the note played detector applies a start. pulse to C1. C1 and C2 are latched into the bistable state vialeads 45 from SG1 and $62, the clock CL is started, and the up-down flipflop 116 is placed in the up mode. The stages C1 and C2 then operate in sequence under. control of the clock and cause gates TGl and-T62 to pass tone signal in sequence. The remainder of the counter stages are not latched into the bistable state and therefore ignore the clock CL, operating as monostable circuits. The count then ripples up the chain very rapidly after passing'Cl and C2 and on achieving stage C20, a pulse is passed via lead-123 to start control 112, which applies a count complete signal to counter stage Cl. Holding down the two notes thus does not cause a repeated strum. But if at least one of the-played keys is released and pressed again, the note played detector 108 produces signals which cause the sequence to repeat, since the note played detector 108 detects depression of a key whether or not other keys are then depressed.

In the up-arpeggio mode, operation is the same as for 4 strum, except that each note played enables the gates SG of octavely related notes, higher in pitch. Actuating a D2 key, for example, renders conductive the D3, D4, D5, etc., gates, along with the D2 gate, just as if the D3, D4, D5 keys had been actuated.

The C1, C5, C9, C13, etc., counter stages are then set into bistable state, and are read out in sequence under control of the clock CL. The tempo for the latter through because ripple time is so short relative to clock-on time.

For arpeggio up and down the output of C20, instead of re-establishing start control 112 in condition to receive a new note, resets the up-down flip-flop 116, which establishes all the counter stages C1-C20 into the down counting mode. The start control 112 is now controlled by C1 via lead 135 in conjunction with the signal on lead 122, so that the start control is prepared for a new start signal if one appears on lead 111, and the down count has been completed through Cl. However, if a note is played while the arpeggio is moving down, a pulse via lead 110 from note plated detector 108 throws up-down'flip-flop 116 into its up mode. A new pulse can still not be inserted at CI, but the count now proceeds up, and any bistable stages cause notes to sound. Whenever a new note is played, up'down flipflop 116 goes into up mode, if it is not already there.

The clock CL has a manual rate control 140. But that rate can be modified by movement of the expression pedal of an organ, by means of an expression control 141. The latter increases clock rate as a function of loudness called for by the expression pedal.

The start control 112 can operate in two states. It can, in one state, prevent C1 from accepting a further pulse, after an arpeggio has started, until control 112 has been reset by a pulse on lead 123 in the up arpeggio mode, or by a pulse on lead 135 in conjunction with information on lead 122 in the up-down arpeggio mode. In this state when an up arpeggio has been started it cannot be modified untilit has been completed. If in the up-down arpeggio mode, and in the down count condition, the actuation of a key will reverse the direction of the arpeggio, but will have no effect on C1.

In the other state, the start control 112 does not prevent C 1 from accepting additional pulses from the note played detector 108 via leader 110 and 111 of FIG. 4. Therefore each time a note is played a new start pulse is introduced into C1 and this pulse is free to proceed up the counter chain. Due to this condition of start control 112, multiple stages of the counter, which are in the bistable state due to the actuation of a key, can be read out simultaneously. The identities of the stages that are read out simultaneously are variable and under control of the operator by his actuation of additional keys during the counting sequence. Since each bistable stage that is read out sounds the note or notes present at the corresponding signal gate 50 through the corresponding tone gate TG, multiple notes can be played and the combination of these notes controlled by the operator. This is called the multi-tone effect, since multiple notes can be heard simultaneously or plural arpeggios canbe proceeding simultaneously. Whether start control 112 will operate in the normal or the multi-tone mode is determined by control 144.

In FIG. 5 is illustrated the tone signal paths of the present system. The signal gates SG l-SG20 pass signals from the sources 13-72, each gate handling three notes, or in effect constituting three gates with a single output. That single output for each of SGl-SG20, (SG21 handles only signal 73 and its output is summed to SG20 output), is applied to its tone gate, so that twenty tone gates TGl-TGZO are required.

' Ten amplifiers 105 convey the outputs of the 20 tone gates to a distributed tone color filter DF, which is well known, per se, from which two groups of tone colored signals are taken, string tones on lead 147 and flute tones on lead 148.

The string tones proceed to two piano tone filters, No. 2 and No. 3, of diverse tonal characteristics, while the flute tones on lead 148 proceed to a third piano filter, No. l. The outputs of piano filters No. 1, No. 2, No. 3 are summed at node 150, and lead via tab switches TB to volume control 151 and thence to the amplifiers 15 and loudspeakers 16 of the organ, shown on FIG. 1.

The flute tones on lead 148 proceed to a harp filter 152 and a harpsichord filter 153. To the latter is also supplied string tone from lead 147, and a banjo filter 154 is likewise supplied. The output of the harp filter is supplied via lead 155 directly to node 150, and the output of piano filter No. 3 via common gate 126 to the output of guitar filter 156 and harp filter 152. The guitar filter is supplied with the output of the harp filter. Common gate 126 supplies a pluck effect to the initial moments of a guitar or harp note. Common gate 126 is turned on with an output of any tone gate TGl-TG20, as evidenced by lead (FIG. 4), and its sustain time is controlled from bus 125. The tone filtering system is per se well known, and forms no part of the present invention, and, accordingly, specific circuit details are not supplied.

Proceeding now to discuss circuit details for implementing the logic of FIG. 4, in FIG. 2, 200 is a source of voltage, 11.5 v., which is connected to three key switchesSl, S2, S3, in parallel-The gates 72 are all the same, so that only one will be described. All the gates derive signal inputs at 201, in the form'of square waves, positively going, and the outputs of the three gates are applied via a common lead 203 to a tone gate 36. The applied DC. voltage proceeds, when S1 is closed, via diode 204 to charge a capacitor C1 via high reactance 206. Discharge of Cl is under control of the tone source, a square wave 207'of the proper frequency for the pitch called for by the key switch S]. C 1 therefore slowly charges while the square wave 207 blocks diode 208, and then discharges rapidly when diode 208 is unblocked. The resultant wave on lead 203 is 209.

Closure of switch S1 also supplies positive voltage via diode 210 and lead 211 to a gate of corresponding nomenclature, one octave higher in pitch, and so on through all such gates. For the DC. voltage supplied by key switch S1 can be substituted a voltage arriving via lead 212 from a gate of the same nomenclature, but of one octave lower pitch. 4

In the strum or normal mode of playing it is desired that higher octaves not be primed when a note of a lower octave is played. To defeat transfer of signal on lead 211, 4.5V can be supplied at W, which renders diode 213 conductive and shorts out lead 211. Any one or more of the three gates, herein denominated a signal gate, when energized via a key switch, as S1, or via a lower octave key switch from a line 212, transfers DC. voltage on lead 74 to a counter flip-flop 71 of counter chain 13, that voltage being applied to the collector of transistor Q1, having an emitter at 4.5V, and a base connectedto lead 215 which proceeds to, selectively, clock CL or -25V., according to the position of switch 130, FIG. 4. If the -25V. supply is applied O1 is held cut off, which implies that the base of O2 is supplied with the steady voltage on lead 74, while a key of three note gate 72 is depressed and remains conductive, its

9 emitterbeing at -4.5V. Incoming leads to the typical stage 71 are 1160 and 117a. With 25.V applied via lead 215 the counter stage 71 is inoperative to count, and this applies to all counter'stages. But when a key switch is closed, the'lead 74 applies a positive voltage to the base of Q2, which generates a drop in voltage at its collector, which in turn appears as a transient pulse at the base of transistor 220 of tone gate 36, transient because of coupling capacitor 221. Because transistor 220 is PN P this pulse turns the transistor transiently on, and passes current into the diodes 222, 223 of linear gate 224, via l.megohm resistances 225, 226, respectively. The lineargate is per se well known. It is normally non-conductive, and is rendered conductive as a function of bias current applied to'the anodes of its two diodes 222, 223. When transistor 220 passes current capacitor Cu is charged positively, and immediately commences to discharge. Part of the discharge, at least, takes place via the gate and-turns the gate on. There is also a discharge path through diode 227 to sustain bus 228. That bus is held at a voltage variable by adjusting slider 229 of potentiometer 230. The terminal 231 of potentiometer 230 is supplied with positive voltage from the note played detector (FIG. 3B.) terminal 81 and the potentiometer 230at its low voltage end is at -.-4.5V,. It follows that the 4.5V. biases the gate 224 off through diode 227, but when a note is played the voltage at point 229 rises. The rate of discharge from Cn is thus modified according to the'position of slider 229, which provides a discharge path in-parallel with the gate 224. If the slider is at 10.V for example, there is no by-pass and the gate has a long sustain, but if the voltage is at 4.5 V. sustain is very short. The output of tone gate 224 may be one, two, or three notes, depending on which of S1, S2, S3 are closed, but since the gate is linear no intermodulation occurs. Clearly, in theory, the system could have been devised to utilize one, two, four or five signal gates per tone gate, the actual number, three, being a compromise choice.

If the clock is connected to terminal T, the counter is permitted to count and each stage acts as a bistable or'monostable flip-flop depending on whether or not there is voltage applied to the stage on lead 74 via one, two or all of the keyswitches 51, 52 or 53. Referring to counter flip-flop 71 of FIG. 2, the initial state of each stage (no keys activated) is Q1 on and 02 off. The actuation of a key switch and resulting application of voltage to the collector of 01 does not change the state of the flip-flop but does provide the necessary supply to make the stage act as a bistable flip-flop. Each stage is read out by the application of a positive ripple pulse either on lead 117a or 116a which is coupled to the base of Q2, and saturates that transistor. This changes the state of this stage and provides a negative step at the collector of Q2 which is coupled to transistor 22@ in the tone gate andsounds the corresponding note.,The next positive clock pulse that appears at terminal T saturates Q1 and changes the state of the flip-flop. This transition provides a positive step at the collector of Q2 which appears at terminal G as a positive pulse and is connected to ll 17a of the preceding stage and 116a of the succeeding stage. Depending on the state of the up down flipflop, the succeeding or preceding stage is then provided with a positive ripple pulse which causes that stage to be read out or rippled through.

If there is no latch in voltage on lead 74, reception of a ripple pulse at the base-of 02 will saturate it only for the duration of that pulse, whichis'too short to activate the note gate transistor 220. Upon coming out of saturation this stage transmits a ripple pulse to the next counter stage. One of the leads 130, 131 may be connected to -4.5 V. If so ripple, pulses are grounded by one of the diodes D1, D2 and do not reach the base of ()2; thus the voltage condition of leads 130, 131 control-the direction in which ripple pulses will progress, either up or down the counter. Essentially, each stage transmits ripple pulses both up and down, but one of these pulses is inhibited and the other not, to establish the direction of the count.

When no keys are actuated there is no current-flow through resistors 241 and 242 which hold Q10 (FlG. 3B)off because its base and emitter are at the same voltage. .U is a supply terminal forall key switches. If

one of these is closed, current flows from terminal 240 through'resistances 241, 242, to terminal U, lowering the voltage at the base of 010, which then fires, passing 11.5 V. to the sustain bus 231 (FIG. 2). At the same time a negative pulse is applied to the base of transistor 242, forming part of a monostable flip-flop with transistor 243, which transmits a pulse on lead 244 via capacitor 245. This pulse is applied to lead 116a of counter stage 1 (FIG. 2), and starts a count. It is also required that the note played detector supply D.C. tothe start control 112 and operate bias to the clock CL and a reset pulse to the up-down flip-flop 116 to assure that it is in the up state. The transistor 242 supplies a pulse via lead 250'to the base of the transistor 251 of the updown flip-flop, which resets the latter. The clock derives its.D.C., so long as any key switch KS is closed, from terminal S (FIG. 3B) of the note played detector 108, via lead 254 to the base'of transistor'255. The latter normally has no voltage applied, and is cut off so that the clock cannot operate. When positive-voltage is supplied to the base of transistor 255 of clock CL, that transistor is biased on and the clock, consisting of a multivibrator, can proceed to oscillate. lts timing or frequency is set by the value of resistance 257, which sets the bias for transistor 255. An alternate-pedal controlled clock is illustrated in FIG. 6;

The output of clock CL proceeds via amplifier I and lead 26l to the upper contact of switch S4. lf-the upper switch-contact is closed' the output pulses proceed to lead 262, and thence to all the counter-stages. if the switch arm S4 is down -25 V. is applied tolead 262, via lead 263 and the counter does not count.

When no keys are actuated the start control 112 is forced into the start state in which transistor 281 is off and 270 is on. This state is insured because, with no keys actuated, lead 259 is at 4.5 V, which prevents transistor 2811 from being on. The state of the up-down flip-flop is not forced under these conditions, and

therefore it can be either in the up or down count state.

When one or more keys are actuated the note played detector provides collector supply voltage to transistor 270 of the start control via lead 259 but does not change the state of the start control. Therefore, the collector of transistor 281i is high, which provides a reverse bias on diode D1 of counter stage 1 (71 in FIG. 3A). This permits the introduction of the positive pulse from the note played detector on lead 294 which starts the counter counting. At the same time, a positive pulse is fed from the note played detector 108 via lead 250 to the base of transistor 251 of the up-down flip-flop 116, to set it in the up count state. Now that these two controls are set the counter begins to count up.

The purpose of the start control 112 is to prevent more than one pulse from being introduced into the counter from the note played detector while a count sequence is in progress. This is accomplished by feeding the output of counter stagel to the start control flip-flop via lead 273. This pulse is directed via diodes 283 and 283A and leads 271 and 271A. These leads are connected to the down control bus and up control bus, respectively, such that when in the up count state, the output of counter stage 1 is directed to the base of transistor 281. This saturates that'transistor and changes the state of the start control 112 to keep transistor 281 saturated, which places a forwardbias on diode D1 of counter stage 1. Diode Dl shunts any input pulse on lead 244 to -45 V an prevents it from operating counter stage- 1. If in the strum or the up arpeggio mode, the output of counter stage 20 is fed via lead 275 and'switch 55 to the base of transistor 270 which satuis constant, regardless of voltage across C22. When transistor Q14 turns on, the negative step at its emitter is coupled via capacitor 22 to the base of transistor 01 1 which turns that transistor off by driving its base to approximately -9 v. Transistor Q11 cannot turn on again until capacitor 22 charges up .to approximately 4 V. This charging period is controlled by the current from constant current source 019 and therefore this source controlsthe frequency of the clock. The negative step at the collector of transistor Q11 when the transistor turns on, is coupled via transistor Q12 and capacitor C1 to the base of transistor Q13 which turns that transistor and transistor Q14 off. The period of this section rates that transistor and changes the state of the start control flip-flop so that it will allow a new pulse to be introduced into the counter chain. This is done because stage 20 represents the end of an up count sequence.

If, however, the device is in the up-down mode, S5 is open and the output of stage 20 is not fed to the base of transistor 270. Instead the second output from stage 1, that occurring while the up-down flip-flop is in the down count state, is directed to the base of transistor 270 via lead 273 and diodes 283 and 283A, and leads I 271 and 271A. This changes the state of the start control flip-flop so that it will permit the introduction of a new pulse into the counter chain, which is necessary because the second output of counter stage 1 indicates the end of an up-down count sequence.

in the multi-tone mode, switch 280 is opened, allowing the emitter of transmitter 281 to float, which prevents lead 282 dropping its potential, so that ripple pulses can be introduced at any time. This implies that' counter. If the system is in the up-down mode and pulses are introduced on the way down, the count direction will be'reversed simultaneously with their introduction.

It is not illustrated, but if there were separate up and down counters, new pulses could be introduced into each at any time, producing simultaneous up and down arpeggios. In the present system the counter must be either proceeding up or proceeding down, and any key closure occurring while the counter is counting down reverses the direction of travel.

While the simple clock of FIG. 3B is suitable generally, an alternative more sophisticated clock is provided in FIG. 6, which has its-rate controlled in two modes or by two complementary controls.

Q11 to Q14 represents an astable multivibrator of conventional character per se, having its last stage Q14 coupled to its first stage Q11 via a capacitor C22. The frequency of the oscillator is determined by the current injected into thecapacitor 22, which is controlled by transistor Q19. The latter operates as a constant current source, i'.e., as if it possessed sufficiently high interof the cycle (Q13 and Q14 off) is not variable and is determined by the time constant of C1 and R3. When the base of transistor Q13 recovers from the negative pulse from transistor O11, O13 turns on which turns on Q14 and couples a negative step from the emitter of Q14 to the base of Q11, which is the beginning of another cycle.

The transistors O15, O16 constitute a pulse amplifier and wave shaping circuit which is conventional per se,

and therefore is not described in detail.

nal resistance that current flow into the capacitor C22 4 When a note is played +1 1.5 V. is applied to terminal 290, from note played detector 108. A current path is then provided through lead 291, variable resistance 292, diode 293, resistance R21, the emitter of transistor Q19, the collector of Q19, capacitor C22, the emitter of Q14, and back to 4.5 V. When the transistor is to be charged, Q14 is conductive, so that effectively the charge on the capacitor 22 isreferenced to 4.5 V.

The current delivered by Q19 is In the equation, VB isthe voltage at the base of Q9, VBE the voltage drop base to emitter of transistor Q19, VD the drop in diode 293 and R21, R28 the values of the resistances in series with transistor Q19, and all are constant. The voltage at the emitter of 019 will follow the voltage at the base of Q19, less about 0.5 V. so that by controlling the base voltage the current flow into C22 can be controlled and will remain constant regardless of the instantaneous voltage on the capacitor, and further this current can be controlled by varying the circuit resistance, i.e., at R28.

A transistor Q20 has its collector connected to the collector of Q19, its base maintained at low voltage via R22, R23, and its collector coupled by capacitor C24 to the terminal 290, which is supplied with +1 1.5 V, when and only when a note is played. Since the emitter of Q20 is connected to 4.5 V, and the base is connected via R23 to 50 V, if there is no voltage on lead 291) (no keys played) transistor Q20 turns on thereby holding the base of Q11 at 4.5 V. This stops the clock when no keys are played and assures the same starting conditions on the clock. Capacitor C24 provides a positive pulse at the base of Q11 when the first key is played to sync the clock to the playing of the first key or keys.

A variable voltage divider is provided in terms of R19 and Q18, the latter having its bias controlled by R17, R18, acting as a voltage divider. Current flow into the base of Q18 determines its resistance so that it is, effectively, a variable resistance controlled by Q17. The latter has its emitter connected to a known constant voltage, its collector connected directly to the base of Q18, and its base connected to a source of voltage controlled R28, manually controlled. If BS is closed, a bucking trol voltage DC. is applied, it is routed to the TI leads of counter'stages C17,C18, C1-9. However, a gate of S618 will be routed via R1, R2 or R3 to turn on 031,

- which removes the down control voltage from T117, so

hence its collector voltage. Accordingly, the position of Y the expression pedal EP controls the resistance of 018, which in turn controls the bias of 019 and hence current flow into C22.

As the expression pedal is pressed downward, the

loudness of the organ increases. Similarly, the voltage at the base of Q21 increases and current flow out of Q19 increases, increasing arpeggio rate. The pedal of the organ thus becomes a useful and convenient device for changing rate of arpeggiation as the arpeggio proceeds, up or down, and the expedient is musically sound because soft music is appropriately associated with slow arpeggio, and vice versa. Of course, other devices may be substituted for the pedal. For example, a knee operated potentiometer may be employed. The crucial point is to provide a voltage controlled clock such that it maybe controlled while the hands are occupied with playing of the organ, and useof the pedal produces a particularly pleasing effect, musically. I 1

It is desirable to prevent the top note in an arpeggio from being played twice, when the present system is in the up-down mode. If the top note played pertains to counter stage C20, there is no problem, since only'up going pulses affect this stage and therefore there can be no repetition of the top note. But, for example, if the top-note pertains to counter stage No. 119, the system will play that top note, ripple through to stage No. in negligible time, and back to No. 19.. Therefore the top notes will play twice with negligible time interval. This distorts the tempo of the .arpeggio.

To solve the problem of double top note pulses in the up-down mode, the key switches which pertain to counter 20 (and note No. 73), provide a voltage on lead 300 via isolating resistances R12, R15,'R18, R21 (FIG. 7). Those key switches pertaining to counter stages No. 19 and No. 20 provide voltage at lead 301, and those key switches pertaining tocounter stages No. 18 and No. 19 and No. 20 to lead 302, all via appropriate ones of isolating resistances RllR2ll, inclusive.

There are three transistor gates, O31, Q32 and 033, which are of NPN type, and have their collectors commonly connected to DC, the down control voltage from the up-down flip-flop 16 (see FIG. 3B), viaload resistances R22, R24, R26. The emitters of the three transistors are commonly connected directly to -4.5 V. and the collectors respectively connected via resistances R23, R and R27 to the bases of the Q1, stages of the C17, C18 and C19 counter stages, labelled Tl in FIG. 2, which illustrates one typical counter stage.

The device is inactive while the arpeggio is proceeding up, since DC is not available. When the down conthat the stage T117 can be free to operate normally in the down arpeggio. Similarly, gate voltage from signal gate SG19 will turn on 031 andQ32, removing the down control voltages from T117 and T118, and a gate voltage of SG20 will remove down control voltage from terminals T117, T118, TI19, by turning on O31, O32, 033. Thus, the down control voltage appears only on the counter corresponding to the highest note played, regardless of which of the Nos. 17, 18, 19 or 20 tone gates is' involved.

The transistors O31, O32, Q33, when open or unfired, permit the DC. voltage to proceed to the TI bases thereby preventing corresponding notes from sounding, but when saturated by a voltage from SO18,

SGI9 or SG20, they remove the control from the TI lead, whereupon'ffthe corresponding counters can re- .spond to the clock and enable production of sound.

It follows that if and only if a No. 20 gate is keyed on, will counter stages No. 17,,No. 18,- No. 19 be able to sound a note during down arpeggio. If aNo. 19 gate is the highest keyed on, gates No. 17 andNo. 18 will be able to sound in down arpeggio, but not No. 19, and if gate No. 18 is the highest keyed on, stage No. 17 will be able to-sound in down arpeggio but not No. 18.

The down control voltage appears at the counters only for the highest note played, only on the way down. For a note in'SG20, no controls are needed, and if 5619 and SG20 are energized simultaneously, $619 will sound on the way down. But if, for example, S619 is the highest note played, it must be silent on the way down and sound only on the way up.

Operation of the present system is summarized as follows. The up-down counter necessary to produce sequential pulsing consists of twenty counter flip-flops,

illustrated in FIG. 2. Each of these flip-flops has two modes of operation, which depend onthe state of the three (or four in the case of stage 20) organ key switches associated with that stage. If one or all of these key switches are closed (or in the case of arpeggio any key associated with a lower note that is octavely related to the notes associated withthe stage under consideration) the flip-flop acts as a bistable flip-flop with initial state of 01 on, Q2 off. If none of these keys is depressed the flip-flops act as monstable flip-flops with an operating time of approximately 30 microseconds. In

either case the initial condition of the flip-flop is Q1 on and Q2 off. In strum and arpeggio modes of operation, but not normal mode, the trigger input T is a 10 volt square wave with short duty cycle. Each stage. has two inputs which provide the means to switch out of the initial state: one is used for the up count and one is used for the down count. These inputs require a positive pulse, and have means (diodes I)1 and D2) tocancel any attempt to switch the state of the flip-flop through either or both inputs. These stages are interconnected, as shown on FIG. 3, with the output of each stage (Gn for'the Nth stage) feeding to the up count input of the next stage (Un+l) and also to the down count input of i the preceding stage (Dn-l Stage 1 receives the first pulse at its up count input (1],) from the note played detector, as shown in FIG. 3. The clock is also synchronized with this note played detector so that the-first clock pulse occurs simultaneously with the playing of a note and the switching of stage 1. An-up-down flipflop is also set in the up count mode" from the note played detector. When the output of stage 1 (G1) has a positive transient it switches stage 2 via the up count input (U2). This switching of stage 2 will take place either at the next clock pulse if stage 1 has been energized (that is if the conditions were met to make stage 1 act as a bistable flip-flop) and in amuch shorter time (the operating time of the monostable) if stage 1 has not been energized. This sequence is repeated until the counter reaches and switches stage at which time the counting stops if the system is in the strum or up arpeggio mode. If it is in the up-down arpeggio mode G20 is connected to the down count input of stage 19 (D19) and to the up-down flip-flop which changes the state of this flip-flop to the down count state, and conditions the counter for down count. The pulse introduced into stage 19 by stage 20 is now free to proceed down the chain in the same manner as the up count pulse proceeded up.

The start control (FIG. 3) determines when a start pulse can be applied to the up count input of stage 1. This control has four inputs, two of which are driven by G1 and each controlled by the up-down flip-flop. If we are in the up count operation a positive pulse at G1 will set the start control so that no new pulsecan be introduced. If we are in the down count mode a positive pulse from G1 will set the start control so that new pulses can be introduced. If we are in the up arpeggio or strum, stage No. 20 is connected to the start control so that after the up-down counter has counted up through stage No. 20, another pulse can be introduced into stage 1. When in theup down arpeggio mode the connection between stage No. 20 and the start control is broken so that no new pulses will be introduced into stage 1 until the down count is complete. In the multitone mode, the start control is essentially disabled so that a new pulse can be introduced at any time.

In the normal mode switch S1 disables the up down flip-flop through diode D3 and places the start control in a state so that no pulses can be introduced into stage 1. It therefore disables the up down counter. Now any key played will provide current through I of the counterflip-flop which will saturate Q2 and provide a negative pulseO This current is not diverted through Q1 because the trigger inputhas now been switched and the trigger is now a negative voltage which will prevent Ql from latching in an on position. A gating pulse is therefore passed by the counter stage operating as an amplifier.

What is claimed is:

1. In combination, a multi-stage counter, the stages of said counter being normally monostable devices and of time constant of the order of microseconds, means for selectively transforming any of said stages to a bistable device, means for at will controlling the time of transfer of said devices when bistable, means responsive to actuation of afirst control device for initiating a complete count of said counter from the first stage of said counter through to a terminal stage of said counter, and means responsive to actuation of a further control device during a count for initiating a further count of said counter from said first stage to said terminal stage without interrupting the first referred to count.

2. The combination according to claim 1, wherein said terminal stage is said first stage and said counter is an up-down counter.

3. The combination according to claim 2, wherein is included means responsive to actuation of said further control for reversing the direction of count of said counter from down to up.

4. The combination according to claim 3, wherein said counter includes stages two to n, wherein n is the ultimate stage of said counter, wherein each of the included stages has a normal state, and means for providing an up transfer pulse to the next higher stage and a down transfer pulse to the next lower stage on each reset of said included stages, and means for selectively inhibiting the up and the down transfer pulses of all said stages simultaneously.

5. In combination, a multi-stage assynchronous counter, a clock, the stages of said counter being normally monostable devices having predetermined time constants, set input and a time delayed reset output means responsive to the reset condition of each stage of said counter for automatically transferring a set pulse to at least one adjacent stage of said counter, voltage responsive means for at will converting any selected ones of said stages to bistable stages, and means responsive only to said clock for resetting said bistable stages. I

6. The combination according to claim 5, wherein said counter is an up-down counter.

7. The combination according to claim 6, wherein means is provided for automatically initiating a down count of said counter inresponse to completion of an up count of said counter.

8. The combination according to claim 7, wherein means is provided for initiating an up count of said counter during said down count of said counter.

9. The combination according to claim 5, wherein means is provided for initiating a complete further count of said counter during a count of said counter.

10. The combination according to claim 5, wherein said clock is normally inoperative, and wherein is provided means for at will rendering said clock operative.

11. The combination according to claim 5, wherein said counter is arranged to complete its up count in response to application of a triggering pulse to an initial stage of said counter.

12. The combination according to claim 6, including control voltage responsive means for selectively conditioning said up-down counter as an up counter and as a down counter.

13. The combination according to claim 12, wherein means is provided for supplying said control voltage in response to completion of an up count of said counter to condition said counter to become a down counter.

without interrupting said last mentioned count of said counter. I

18. The combination according to claim 6, wherein each of said stages on reset transfers a set pulse to the next preceding and the next succeeding stage of said counter, and means for inhibiting one of said last named set pulses.

19. The combination according to claim 6, wherein means is provided for initiating each complete count of said counter only as an up count of said counter. 

1. In combination, a multi-stage counter, the stages of said counter being normally monostable devices and of time constant of the order of 30 microseconds, means for selectively transforming any of said stages to a bistable device, means for at will controlling the time of transfer of said devices when bistable, means responsive to actuation of a first control device for initiating a complete count of said counter from the first stage of said counter through to a terminal stage of said counter, and means responsive to actuation of a further control device during a count for initiating a further count of said counter from said first stage to said terminal stage without interrupting the first referred to count.
 2. The combination according to claim 1, wherein said terminal stage is said first stage and said counter is an up-down counter.
 3. The combination according to claim 2, wherein is included means responsive to actuation of said further control for reversing the direction of count of said counter from down to up.
 4. The combination according to claim 3, wherein said counter includes stages two to n, wherein n is the ultimate stage of said counter, wherein each of the included stages has a normal state, and means for providing an up transfer pulse to the next higher stage and a down transfer pulse to the next lower stage on each reset of said included stages, and means for selectively inhibiting the up and the down transfer pulses of all said stages simultaneously.
 5. In combination, a multi-stage assynchronous counter, a clock, the stages of said counter being normally monostable devices having predetermined time constants, set input and a time delayed reset output means responsive to the reset condition of each stage of said counter for automatically transferring a set pulse to at least one adjacent stage of said counter, voltage responsive means for at will converting any selected ones of said stages to bistable stages, and means responsive only to said clock for resetting said bistable stages.
 6. The combination according to claim 5, wherein said counter is an up-down counter.
 7. The combination according to claim 6, wherein means is provided for automatically initiating a down count of said counter in response to completion of an up count of said counter.
 8. The combination according to claim 7, wherein means is provided for initiating an up count of said counter during said down count of said counter.
 9. The combination according to claim 5, wherein means is provided for initiating a complete further count of said counter during a count of said counter.
 10. The combination according to claim 5, wherein said clock is normally inoperative, and wherein is provided means for at will rendering said clock operative.
 11. The combination according to claim 5, wherein said counter is arranged to complete its up count in response to application of a triggering pulse to an initial stage of said counter.
 12. The combination according to claim 6, including control voltage responsive means for selectively conditioning said up-down counter as an up counter and as a down counter.
 13. The combination according to claim 12, wherein means is provided for supplying said control voltage in response to completion of an up count of said counter to condition said counter to become a down counter.
 14. The combination according to claim 5, wherein means is provided responsive to completion of a count of said counter for setting said counter in condition for a further complete count of said counter.
 15. The combination according to claim 5, wherein means is provided for terminating operation of said counter upon completion of an up count of said counter, and voltage responsive means for initiating a further up count of said counter.
 16. The combination according to claim 6, wherein voltage responsive means is provided for at will reversing the direction of count of said counter during a down count of said counter.
 17. The combination according to claim 6, wherein means is provided for at will commencing a further count of said counter during count of said counter without interrupting said last mentioned count of said counter.
 18. The combination according to claim 6, wherein each of said stages on reset transfers a set pulse to the next preceding and the next succeeding stage of said counter, and means for inhibiting one of said last named set pulses.
 19. The combination according to claim 6, wherein means is provided for initiating each complete count of said counter only as an up count of said counter. 